The present invention relates to a semiconductor device, and, more particularly, to a method of forming a line pattern array, a photomask having the same and a semiconductor device fabricated thereby.
In order to implement a semiconductor device having a circuit pattern on a wafer, a microlithography process is performed. The microlithography process includes a process of forming a photomask through a mask pattern layout to be implemented on a transparent substrate. The mask pattern is transferred onto a photoresist layer deposited on the wafer by an exposure process using the mask. In such a pattern transferring process, it can be difficult for a wafer pattern formed on the wafer, namely, a photoresist pattern, to have a line width corresponding to a designed target critical dimension (CD).
In case of a memory semiconductor device such as a DRAM device or a NAND flash device, it has a cell area in which memory cells are repetitively arranged. Line patterns, which form conductive layers such as gate patterns of transistors in the cell area, are repetitively arranged with a constant line width and spacing. Since the line patterns are repeated at a substantially same pitch in the cell area, there are several equal patterns around one line pattern.
However, in case of a line pattern arranged at an outermost side, such an outermost line pattern may be adjacent to other cell line patterns in one direction with the same width and space, however, the line pattern may not be adjacent to such the same line patterns or be adjacent to other cell line patterns which have a substantially different line width and space in the opposite direction. For example, a dummy line pattern, which has a larger line width and a first space larger than a second space of the cell line patterns, is arranged outside the outermost line pattern. The dummy line pattern is introduced to suppress an influence of the local etch loading effect on the outermost line pattern in a selective etching process which is performed after the pattern transferring process.
The outermost line pattern is partially influenced by the dummy line pattern because an optical circumstance, for example, the optical proximity effect (OPE) during an exposure process, at the outermost line pattern is different from that at other cell line patterns which are inside. Since the outermost line pattern is transferred under such an optical effect, it is difficult to secure a CD of a wafer pattern, for example, a photoresist pattern, corresponding to a designed target line width. Further, in case that it is necessary to secure the line width of the outermost line pattern larger than that of the inner line patterns, it is difficult to obtain such a wide width of the outermost line pattern, and then the outermost line pattern finally formed on the wafer may have a line width smaller than the target line width because the line width of the outermost line pattern formed on the wafer does not get substantially larger although the layout of the outermost line pattern is set to be a wide line width on a mask.
Considering an exposure contrast at the time of exposing the outermost line pattern, the exposure contrast is substantially influenced by a larger pitch of the dummy line pattern arranged outside the outermost line pattern. Thus, if the line width of the outermost line pattern is intentionally changed, the exposure contrast according to the change of the line width is limited. Therefore, a change of the line width of a substantially formed wafer pattern according to the line width change of the outermost line pattern is excessively limited. Also, an excessive expansion of the line width of the outermost line pattern can cause an undesired bridge defect between the outermost line pattern and the dummy pattern. Further, since the pitch of the dummy line pattern arranged outside the outermost line pattern is set considering an etch loading effect, it is difficult to change the pitch of the dummy line pattern arbitrarily. Thus, in a state that the change of the pitch of the dummy line pattern is limited, the control of the line width of the outermost line pattern is getting more difficult in a cell line pattern array.
Nonetheless, considering an operation of an actual memory device, it is required for the outermost cell line pattern to have a line width larger than that of other inside cell line patterns in order to suppress disturbance with the other inside cell line patterns or improve a line resistance of the outermost cell line pattern. Accordingly, a method of controlling the line width of the outermost cell line pattern which is adjacent to the dummy line pattern of which pitch is limited, that is, a method of making a wider line width of the outermost cell line pattern, is required.